Analysis & Synthesis report for DE0_NANO
Mon Jun 19 20:10:05 2017
Quartus Prime Version 15.1.0 Build 185 10/21/2015 SJ Lite Edition


---------------------
; Table of Contents ;
---------------------
  1. Legal Notice
  2. Analysis & Synthesis Summary
  3. Analysis & Synthesis Settings
  4. Parallel Compilation
  5. Analysis & Synthesis Source Files Read
  6. Analysis & Synthesis Resource Usage Summary
  7. Analysis & Synthesis Resource Utilization by Entity
  8. General Register Statistics
  9. Multiplexer Restructuring Statistics (Restructuring Performed)
 10. Port Connectivity Checks: "VGA_DRIVER:driver"
 11. Post-Synthesis Netlist Statistics for Top Partition
 12. Elapsed Time Per Partition
 13. Analysis & Synthesis Messages



----------------
; Legal Notice ;
----------------
Copyright (C) 1991-2015 Altera Corporation. All rights reserved.
Your use of Altera Corporation's design tools, logic functions 
and other software and tools, and its AMPP partner logic 
functions, and any output files from any of the foregoing 
(including device programming or simulation files), and any 
associated documentation or information are expressly subject 
to the terms and conditions of the Altera Program License 
Subscription Agreement, the Altera Quartus Prime License Agreement,
the Altera MegaCore Function License Agreement, or other 
applicable license agreement, including, without limitation, 
that your use is for the sole purpose of programming logic 
devices manufactured by Altera and sold by Altera or its 
authorized distributors.  Please refer to the applicable 
agreement for further details.



+----------------------------------------------------------------------------------+
; Analysis & Synthesis Summary                                                     ;
+------------------------------------+---------------------------------------------+
; Analysis & Synthesis Status        ; Successful - Mon Jun 19 20:10:05 2017       ;
; Quartus Prime Version              ; 15.1.0 Build 185 10/21/2015 SJ Lite Edition ;
; Revision Name                      ; DE0_NANO                                    ;
; Top-level Entity Name              ; DE0_NANO                                    ;
; Family                             ; Cyclone IV E                                ;
; Total logic elements               ; 82                                          ;
;     Total combinational functions  ; 82                                          ;
;     Dedicated logic registers      ; 47                                          ;
; Total registers                    ; 47                                          ;
; Total pins                         ; 87                                          ;
; Total virtual pins                 ; 0                                           ;
; Total memory bits                  ; 0                                           ;
; Embedded Multiplier 9-bit elements ; 0                                           ;
; Total PLLs                         ; 0                                           ;
+------------------------------------+---------------------------------------------+


+----------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Settings                                                                                        ;
+----------------------------------------------------------------------------+--------------------+--------------------+
; Option                                                                     ; Setting            ; Default Value      ;
+----------------------------------------------------------------------------+--------------------+--------------------+
; Device                                                                     ; EP4CE22F17C6       ;                    ;
; Top-level entity name                                                      ; DE0_NANO           ; DE0_NANO           ;
; Family name                                                                ; Cyclone IV E       ; Cyclone IV GX      ;
; Use smart compilation                                                      ; Off                ; Off                ;
; Enable parallel Assembler and TimeQuest Timing Analyzer during compilation ; On                 ; On                 ;
; Enable compact report table                                                ; Off                ; Off                ;
; Restructure Multiplexers                                                   ; Auto               ; Auto               ;
; Create Debugging Nodes for IP Cores                                        ; Off                ; Off                ;
; Preserve fewer node names                                                  ; On                 ; On                 ;
; Disable OpenCore Plus hardware evaluation                                  ; Off                ; Off                ;
; Verilog Version                                                            ; Verilog_2001       ; Verilog_2001       ;
; VHDL Version                                                               ; VHDL_1993          ; VHDL_1993          ;
; State Machine Processing                                                   ; Auto               ; Auto               ;
; Safe State Machine                                                         ; Off                ; Off                ;
; Extract Verilog State Machines                                             ; On                 ; On                 ;
; Extract VHDL State Machines                                                ; On                 ; On                 ;
; Ignore Verilog initial constructs                                          ; Off                ; Off                ;
; Iteration limit for constant Verilog loops                                 ; 5000               ; 5000               ;
; Iteration limit for non-constant Verilog loops                             ; 250                ; 250                ;
; Add Pass-Through Logic to Inferred RAMs                                    ; On                 ; On                 ;
; Infer RAMs from Raw Logic                                                  ; On                 ; On                 ;
; Parallel Synthesis                                                         ; On                 ; On                 ;
; DSP Block Balancing                                                        ; Auto               ; Auto               ;
; NOT Gate Push-Back                                                         ; On                 ; On                 ;
; Power-Up Don't Care                                                        ; On                 ; On                 ;
; Remove Redundant Logic Cells                                               ; Off                ; Off                ;
; Remove Duplicate Registers                                                 ; On                 ; On                 ;
; Ignore CARRY Buffers                                                       ; Off                ; Off                ;
; Ignore CASCADE Buffers                                                     ; Off                ; Off                ;
; Ignore GLOBAL Buffers                                                      ; Off                ; Off                ;
; Ignore ROW GLOBAL Buffers                                                  ; Off                ; Off                ;
; Ignore LCELL Buffers                                                       ; Off                ; Off                ;
; Ignore SOFT Buffers                                                        ; On                 ; On                 ;
; Limit AHDL Integers to 32 Bits                                             ; Off                ; Off                ;
; Optimization Technique                                                     ; Balanced           ; Balanced           ;
; Carry Chain Length                                                         ; 70                 ; 70                 ;
; Auto Carry Chains                                                          ; On                 ; On                 ;
; Auto Open-Drain Pins                                                       ; On                 ; On                 ;
; Perform WYSIWYG Primitive Resynthesis                                      ; Off                ; Off                ;
; Auto ROM Replacement                                                       ; On                 ; On                 ;
; Auto RAM Replacement                                                       ; On                 ; On                 ;
; Auto DSP Block Replacement                                                 ; On                 ; On                 ;
; Auto Shift Register Replacement                                            ; Auto               ; Auto               ;
; Allow Shift Register Merging across Hierarchies                            ; Auto               ; Auto               ;
; Auto Clock Enable Replacement                                              ; On                 ; On                 ;
; Strict RAM Replacement                                                     ; Off                ; Off                ;
; Allow Synchronous Control Signals                                          ; On                 ; On                 ;
; Force Use of Synchronous Clear Signals                                     ; Off                ; Off                ;
; Auto RAM Block Balancing                                                   ; On                 ; On                 ;
; Auto RAM to Logic Cell Conversion                                          ; Off                ; Off                ;
; Auto Resource Sharing                                                      ; Off                ; Off                ;
; Allow Any RAM Size For Recognition                                         ; Off                ; Off                ;
; Allow Any ROM Size For Recognition                                         ; Off                ; Off                ;
; Allow Any Shift Register Size For Recognition                              ; Off                ; Off                ;
; Use LogicLock Constraints during Resource Balancing                        ; On                 ; On                 ;
; Ignore translate_off and synthesis_off directives                          ; Off                ; Off                ;
; Timing-Driven Synthesis                                                    ; On                 ; On                 ;
; Report Parameter Settings                                                  ; On                 ; On                 ;
; Report Source Assignments                                                  ; On                 ; On                 ;
; Report Connectivity Checks                                                 ; On                 ; On                 ;
; Ignore Maximum Fan-Out Assignments                                         ; Off                ; Off                ;
; Synchronization Register Chain Length                                      ; 2                  ; 2                  ;
; PowerPlay Power Optimization During Synthesis                              ; Normal compilation ; Normal compilation ;
; HDL message level                                                          ; Level2             ; Level2             ;
; Suppress Register Optimization Related Messages                            ; Off                ; Off                ;
; Number of Removed Registers Reported in Synthesis Report                   ; 5000               ; 5000               ;
; Number of Swept Nodes Reported in Synthesis Report                         ; 5000               ; 5000               ;
; Number of Inverted Registers Reported in Synthesis Report                  ; 100                ; 100                ;
; Clock MUX Protection                                                       ; On                 ; On                 ;
; Auto Gated Clock Conversion                                                ; Off                ; Off                ;
; Block Design Naming                                                        ; Auto               ; Auto               ;
; SDC constraint protection                                                  ; Off                ; Off                ;
; Synthesis Effort                                                           ; Auto               ; Auto               ;
; Shift Register Replacement - Allow Asynchronous Clear Signal               ; On                 ; On                 ;
; Pre-Mapping Resynthesis Optimization                                       ; Off                ; Off                ;
; Analysis & Synthesis Message Level                                         ; Medium             ; Medium             ;
; Disable Register Merging Across Hierarchies                                ; Auto               ; Auto               ;
; Resource Aware Inference For Block RAM                                     ; On                 ; On                 ;
; Synthesis Seed                                                             ; 1                  ; 1                  ;
+----------------------------------------------------------------------------+--------------------+--------------------+


Parallel compilation was disabled, but you have multiple processors available. Enable parallel compilation to reduce compilation time.
+-------------------------------------+
; Parallel Compilation                ;
+----------------------------+--------+
; Processors                 ; Number ;
+----------------------------+--------+
; Number detected on machine ; 8      ;
; Maximum allowed            ; 1      ;
+----------------------------+--------+


+---------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Source Files Read                                                                                                                        ;
+----------------------------------+-----------------+------------------------+-----------------------------------------------------------------------+---------+
; File Name with User-Entered Path ; Used in Netlist ; File Type              ; File Name with Absolute Path                                          ; Library ;
+----------------------------------+-----------------+------------------------+-----------------------------------------------------------------------+---------+
; VGA_DRIVER.v                     ; yes             ; User Verilog HDL File  ; C:/Users/lab user/Desktop/ECE3400_Fall2017/Lab3_template/VGA_DRIVER.v ;         ;
; DE0_NANO.v                       ; yes             ; User Verilog HDL File  ; C:/Users/lab user/Desktop/ECE3400_Fall2017/Lab3_template/DE0_NANO.v   ;         ;
+----------------------------------+-----------------+------------------------+-----------------------------------------------------------------------+---------+


+--------------------------------------------------------+
; Analysis & Synthesis Resource Usage Summary            ;
+---------------------------------------------+----------+
; Resource                                    ; Usage    ;
+---------------------------------------------+----------+
; Estimated Total logic elements              ; 82       ;
;                                             ;          ;
; Total combinational functions               ; 82       ;
; Logic element usage by number of LUT inputs ;          ;
;     -- 4 input functions                    ; 17       ;
;     -- 3 input functions                    ; 3        ;
;     -- <=2 input functions                  ; 62       ;
;                                             ;          ;
; Logic elements by mode                      ;          ;
;     -- normal mode                          ; 40       ;
;     -- arithmetic mode                      ; 42       ;
;                                             ;          ;
; Total registers                             ; 47       ;
;     -- Dedicated logic registers            ; 47       ;
;     -- I/O registers                        ; 0        ;
;                                             ;          ;
; I/O pins                                    ; 87       ;
;                                             ;          ;
; Embedded Multiplier 9-bit elements          ; 0        ;
;                                             ;          ;
; Maximum fan-out node                        ; CLOCK_25 ;
; Maximum fan-out                             ; 47       ;
; Total fan-out                               ; 482      ;
; Average fan-out                             ; 1.30     ;
+---------------------------------------------+----------+


+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Resource Utilization by Entity                                                                                                                                 ;
+----------------------------+-------------------+--------------+-------------+--------------+---------+-----------+------+--------------+-----------------------------+--------------+
; Compilation Hierarchy Node ; LC Combinationals ; LC Registers ; Memory Bits ; DSP Elements ; DSP 9x9 ; DSP 18x18 ; Pins ; Virtual Pins ; Full Hierarchy Name         ; Library Name ;
+----------------------------+-------------------+--------------+-------------+--------------+---------+-----------+------+--------------+-----------------------------+--------------+
; |DE0_NANO                  ; 82 (48)           ; 47 (27)      ; 0           ; 0            ; 0       ; 0         ; 87   ; 0            ; |DE0_NANO                   ; work         ;
;    |VGA_DRIVER:driver|     ; 34 (34)           ; 20 (20)      ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |DE0_NANO|VGA_DRIVER:driver ; work         ;
+----------------------------+-------------------+--------------+-------------+--------------+---------+-----------+------+--------------+-----------------------------+--------------+
Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy.


+------------------------------------------------------+
; General Register Statistics                          ;
+----------------------------------------------+-------+
; Statistic                                    ; Value ;
+----------------------------------------------+-------+
; Total registers                              ; 47    ;
; Number of registers using Synchronous Clear  ; 20    ;
; Number of registers using Synchronous Load   ; 0     ;
; Number of registers using Asynchronous Clear ; 0     ;
; Number of registers using Asynchronous Load  ; 0     ;
; Number of registers using Clock Enable       ; 10    ;
; Number of registers using Preset             ; 0     ;
+----------------------------------------------+-------+


+----------------------------------------------------------------------------------------------------------------------------------------------------------+
; Multiplexer Restructuring Statistics (Restructuring Performed)                                                                                           ;
+--------------------+-----------+---------------+----------------------+------------------------+------------+--------------------------------------------+
; Multiplexer Inputs ; Bus Width ; Baseline Area ; Area if Restructured ; Saving if Restructured ; Registered ; Example Multiplexer Output                 ;
+--------------------+-----------+---------------+----------------------+------------------------+------------+--------------------------------------------+
; 3:1                ; 10 bits   ; 20 LEs        ; 10 LEs               ; 10 LEs                 ; Yes        ; |DE0_NANO|VGA_DRIVER:driver|pixel_count[5] ;
; 4:1                ; 10 bits   ; 20 LEs        ; 10 LEs               ; 10 LEs                 ; Yes        ; |DE0_NANO|VGA_DRIVER:driver|line_count[9]  ;
+--------------------+-----------+---------------+----------------------+------------------------+------------+--------------------------------------------+


+--------------------------------------------------------------------------------------------------------------------------------+
; Port Connectivity Checks: "VGA_DRIVER:driver"                                                                                  ;
+----------------------+--------+----------+-------------------------------------------------------------------------------------+
; Port                 ; Type   ; Severity ; Details                                                                             ;
+----------------------+--------+----------+-------------------------------------------------------------------------------------+
; PIXEL_COLOR_IN[4..2] ; Input  ; Info     ; Stuck at VCC                                                                        ;
; PIXEL_COLOR_IN[7..5] ; Input  ; Info     ; Stuck at GND                                                                        ;
; PIXEL_COLOR_IN[1..0] ; Input  ; Info     ; Stuck at GND                                                                        ;
; PIXEL_X              ; Output ; Info     ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ;
; PIXEL_Y              ; Output ; Info     ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ;
+----------------------+--------+----------+-------------------------------------------------------------------------------------+


+-----------------------------------------------------+
; Post-Synthesis Netlist Statistics for Top Partition ;
+-----------------------+-----------------------------+
; Type                  ; Count                       ;
+-----------------------+-----------------------------+
; boundary_port         ; 87                          ;
; cycloneiii_ff         ; 47                          ;
;     ENA SCLR          ; 10                          ;
;     SCLR              ; 10                          ;
;     plain             ; 27                          ;
; cycloneiii_io_obuf    ; 68                          ;
; cycloneiii_lcell_comb ; 83                          ;
;     arith             ; 42                          ;
;         2 data inputs ; 42                          ;
;     normal            ; 41                          ;
;         0 data inputs ; 1                           ;
;         1 data inputs ; 4                           ;
;         2 data inputs ; 16                          ;
;         3 data inputs ; 3                           ;
;         4 data inputs ; 17                          ;
;                       ;                             ;
; Max LUT depth         ; 4.40                        ;
; Average LUT depth     ; 2.04                        ;
+-----------------------+-----------------------------+


+-------------------------------+
; Elapsed Time Per Partition    ;
+----------------+--------------+
; Partition Name ; Elapsed Time ;
+----------------+--------------+
; Top            ; 00:00:00     ;
+----------------+--------------+


+-------------------------------+
; Analysis & Synthesis Messages ;
+-------------------------------+
Info: *******************************************************************
Info: Running Quartus Prime Analysis & Synthesis
    Info: Version 15.1.0 Build 185 10/21/2015 SJ Lite Edition
    Info: Processing started: Mon Jun 19 20:09:56 2017
Info: Command: quartus_map --read_settings_files=on --write_settings_files=off DE0_NANO -c DE0_NANO
Warning (125092): Tcl Script File DE_NANO_SOPC.qip not found
    Info (125063): set_global_assignment -name QIP_FILE DE_NANO_SOPC.qip
Warning (20028): Parallel compilation is not licensed and has been disabled
Info (12021): Found 1 design units, including 1 entities, in source file vga_driver.v
    Info (12023): Found entity 1: VGA_DRIVER File: C:/Users/lab user/Desktop/ECE3400_Fall2017/Lab3_template/VGA_DRIVER.v Line: 14
Warning (10238): Verilog Module Declaration warning at DE0_NANO.v(32): ignored anonymous port(s) indicated by duplicate or dangling comma(s) in the port list for module "DE0_NANO" File: C:/Users/lab user/Desktop/ECE3400_Fall2017/Lab3_template/DE0_NANO.v Line: 32
Info (12021): Found 1 design units, including 1 entities, in source file de0_nano.v
    Info (12023): Found entity 1: DE0_NANO File: C:/Users/lab user/Desktop/ECE3400_Fall2017/Lab3_template/DE0_NANO.v Line: 11
Info (12127): Elaborating entity "DE0_NANO" for the top level hierarchy
Warning (10034): Output port "LED[7..1]" at DE0_NANO.v(48) has no driver File: C:/Users/lab user/Desktop/ECE3400_Fall2017/Lab3_template/DE0_NANO.v Line: 48
Info (12128): Elaborating entity "VGA_DRIVER" for hierarchy "VGA_DRIVER:driver" File: C:/Users/lab user/Desktop/ECE3400_Fall2017/Lab3_template/DE0_NANO.v Line: 87
Warning (10230): Verilog HDL assignment warning at VGA_DRIVER.v(71): truncated value with size 32 to match size of target (10) File: C:/Users/lab user/Desktop/ECE3400_Fall2017/Lab3_template/VGA_DRIVER.v Line: 71
Warning (10230): Verilog HDL assignment warning at VGA_DRIVER.v(75): truncated value with size 32 to match size of target (10) File: C:/Users/lab user/Desktop/ECE3400_Fall2017/Lab3_template/VGA_DRIVER.v Line: 75
Warning (13034): The following nodes have both tri-state and non-tri-state drivers
    Warning (13035): Inserted always-enabled tri-state buffer between "GPIO_0_D[5]" and its non-tri-state driver. File: C:/Users/lab user/Desktop/ECE3400_Fall2017/Lab3_template/DE0_NANO.v Line: 57
    Warning (13035): Inserted always-enabled tri-state buffer between "GPIO_0_D[7]" and its non-tri-state driver. File: C:/Users/lab user/Desktop/ECE3400_Fall2017/Lab3_template/DE0_NANO.v Line: 57
    Warning (13035): Inserted always-enabled tri-state buffer between "GPIO_0_D[15]" and its non-tri-state driver. File: C:/Users/lab user/Desktop/ECE3400_Fall2017/Lab3_template/DE0_NANO.v Line: 57
    Warning (13035): Inserted always-enabled tri-state buffer between "GPIO_0_D[17]" and its non-tri-state driver. File: C:/Users/lab user/Desktop/ECE3400_Fall2017/Lab3_template/DE0_NANO.v Line: 57
    Warning (13035): Inserted always-enabled tri-state buffer between "GPIO_0_D[19]" and its non-tri-state driver. File: C:/Users/lab user/Desktop/ECE3400_Fall2017/Lab3_template/DE0_NANO.v Line: 57
Warning (13039): The following bidirectional pins have no drivers
    Warning (13040): bidirectional pin "GPIO_0_D[0]" has no driver File: C:/Users/lab user/Desktop/ECE3400_Fall2017/Lab3_template/DE0_NANO.v Line: 57
    Warning (13040): bidirectional pin "GPIO_0_D[1]" has no driver File: C:/Users/lab user/Desktop/ECE3400_Fall2017/Lab3_template/DE0_NANO.v Line: 57
    Warning (13040): bidirectional pin "GPIO_0_D[2]" has no driver File: C:/Users/lab user/Desktop/ECE3400_Fall2017/Lab3_template/DE0_NANO.v Line: 57
    Warning (13040): bidirectional pin "GPIO_0_D[3]" has no driver File: C:/Users/lab user/Desktop/ECE3400_Fall2017/Lab3_template/DE0_NANO.v Line: 57
    Warning (13040): bidirectional pin "GPIO_0_D[4]" has no driver File: C:/Users/lab user/Desktop/ECE3400_Fall2017/Lab3_template/DE0_NANO.v Line: 57
    Warning (13040): bidirectional pin "GPIO_0_D[6]" has no driver File: C:/Users/lab user/Desktop/ECE3400_Fall2017/Lab3_template/DE0_NANO.v Line: 57
    Warning (13040): bidirectional pin "GPIO_0_D[8]" has no driver File: C:/Users/lab user/Desktop/ECE3400_Fall2017/Lab3_template/DE0_NANO.v Line: 57
    Warning (13040): bidirectional pin "GPIO_0_D[10]" has no driver File: C:/Users/lab user/Desktop/ECE3400_Fall2017/Lab3_template/DE0_NANO.v Line: 57
    Warning (13040): bidirectional pin "GPIO_0_D[12]" has no driver File: C:/Users/lab user/Desktop/ECE3400_Fall2017/Lab3_template/DE0_NANO.v Line: 57
    Warning (13040): bidirectional pin "GPIO_0_D[14]" has no driver File: C:/Users/lab user/Desktop/ECE3400_Fall2017/Lab3_template/DE0_NANO.v Line: 57
    Warning (13040): bidirectional pin "GPIO_0_D[16]" has no driver File: C:/Users/lab user/Desktop/ECE3400_Fall2017/Lab3_template/DE0_NANO.v Line: 57
    Warning (13040): bidirectional pin "GPIO_0_D[18]" has no driver File: C:/Users/lab user/Desktop/ECE3400_Fall2017/Lab3_template/DE0_NANO.v Line: 57
    Warning (13040): bidirectional pin "GPIO_0_D[20]" has no driver File: C:/Users/lab user/Desktop/ECE3400_Fall2017/Lab3_template/DE0_NANO.v Line: 57
    Warning (13040): bidirectional pin "GPIO_0_D[22]" has no driver File: C:/Users/lab user/Desktop/ECE3400_Fall2017/Lab3_template/DE0_NANO.v Line: 57
    Warning (13040): bidirectional pin "GPIO_0_D[24]" has no driver File: C:/Users/lab user/Desktop/ECE3400_Fall2017/Lab3_template/DE0_NANO.v Line: 57
    Warning (13040): bidirectional pin "GPIO_0_D[25]" has no driver File: C:/Users/lab user/Desktop/ECE3400_Fall2017/Lab3_template/DE0_NANO.v Line: 57
    Warning (13040): bidirectional pin "GPIO_0_D[26]" has no driver File: C:/Users/lab user/Desktop/ECE3400_Fall2017/Lab3_template/DE0_NANO.v Line: 57
    Warning (13040): bidirectional pin "GPIO_0_D[27]" has no driver File: C:/Users/lab user/Desktop/ECE3400_Fall2017/Lab3_template/DE0_NANO.v Line: 57
    Warning (13040): bidirectional pin "GPIO_0_D[28]" has no driver File: C:/Users/lab user/Desktop/ECE3400_Fall2017/Lab3_template/DE0_NANO.v Line: 57
    Warning (13040): bidirectional pin "GPIO_0_D[29]" has no driver File: C:/Users/lab user/Desktop/ECE3400_Fall2017/Lab3_template/DE0_NANO.v Line: 57
    Warning (13040): bidirectional pin "GPIO_0_D[30]" has no driver File: C:/Users/lab user/Desktop/ECE3400_Fall2017/Lab3_template/DE0_NANO.v Line: 57
    Warning (13040): bidirectional pin "GPIO_0_D[31]" has no driver File: C:/Users/lab user/Desktop/ECE3400_Fall2017/Lab3_template/DE0_NANO.v Line: 57
    Warning (13040): bidirectional pin "GPIO_0_D[32]" has no driver File: C:/Users/lab user/Desktop/ECE3400_Fall2017/Lab3_template/DE0_NANO.v Line: 57
    Warning (13040): bidirectional pin "GPIO_0_D[33]" has no driver File: C:/Users/lab user/Desktop/ECE3400_Fall2017/Lab3_template/DE0_NANO.v Line: 57
    Warning (13040): bidirectional pin "GPIO_1_D[0]" has no driver File: C:/Users/lab user/Desktop/ECE3400_Fall2017/Lab3_template/DE0_NANO.v Line: 61
    Warning (13040): bidirectional pin "GPIO_1_D[1]" has no driver File: C:/Users/lab user/Desktop/ECE3400_Fall2017/Lab3_template/DE0_NANO.v Line: 61
    Warning (13040): bidirectional pin "GPIO_1_D[2]" has no driver File: C:/Users/lab user/Desktop/ECE3400_Fall2017/Lab3_template/DE0_NANO.v Line: 61
    Warning (13040): bidirectional pin "GPIO_1_D[3]" has no driver File: C:/Users/lab user/Desktop/ECE3400_Fall2017/Lab3_template/DE0_NANO.v Line: 61
    Warning (13040): bidirectional pin "GPIO_1_D[4]" has no driver File: C:/Users/lab user/Desktop/ECE3400_Fall2017/Lab3_template/DE0_NANO.v Line: 61
    Warning (13040): bidirectional pin "GPIO_1_D[5]" has no driver File: C:/Users/lab user/Desktop/ECE3400_Fall2017/Lab3_template/DE0_NANO.v Line: 61
    Warning (13040): bidirectional pin "GPIO_1_D[6]" has no driver File: C:/Users/lab user/Desktop/ECE3400_Fall2017/Lab3_template/DE0_NANO.v Line: 61
    Warning (13040): bidirectional pin "GPIO_1_D[7]" has no driver File: C:/Users/lab user/Desktop/ECE3400_Fall2017/Lab3_template/DE0_NANO.v Line: 61
    Warning (13040): bidirectional pin "GPIO_1_D[8]" has no driver File: C:/Users/lab user/Desktop/ECE3400_Fall2017/Lab3_template/DE0_NANO.v Line: 61
    Warning (13040): bidirectional pin "GPIO_1_D[9]" has no driver File: C:/Users/lab user/Desktop/ECE3400_Fall2017/Lab3_template/DE0_NANO.v Line: 61
    Warning (13040): bidirectional pin "GPIO_1_D[10]" has no driver File: C:/Users/lab user/Desktop/ECE3400_Fall2017/Lab3_template/DE0_NANO.v Line: 61
    Warning (13040): bidirectional pin "GPIO_1_D[11]" has no driver File: C:/Users/lab user/Desktop/ECE3400_Fall2017/Lab3_template/DE0_NANO.v Line: 61
    Warning (13040): bidirectional pin "GPIO_1_D[12]" has no driver File: C:/Users/lab user/Desktop/ECE3400_Fall2017/Lab3_template/DE0_NANO.v Line: 61
    Warning (13040): bidirectional pin "GPIO_1_D[13]" has no driver File: C:/Users/lab user/Desktop/ECE3400_Fall2017/Lab3_template/DE0_NANO.v Line: 61
    Warning (13040): bidirectional pin "GPIO_1_D[14]" has no driver File: C:/Users/lab user/Desktop/ECE3400_Fall2017/Lab3_template/DE0_NANO.v Line: 61
    Warning (13040): bidirectional pin "GPIO_1_D[15]" has no driver File: C:/Users/lab user/Desktop/ECE3400_Fall2017/Lab3_template/DE0_NANO.v Line: 61
    Warning (13040): bidirectional pin "GPIO_1_D[16]" has no driver File: C:/Users/lab user/Desktop/ECE3400_Fall2017/Lab3_template/DE0_NANO.v Line: 61
    Warning (13040): bidirectional pin "GPIO_1_D[17]" has no driver File: C:/Users/lab user/Desktop/ECE3400_Fall2017/Lab3_template/DE0_NANO.v Line: 61
    Warning (13040): bidirectional pin "GPIO_1_D[18]" has no driver File: C:/Users/lab user/Desktop/ECE3400_Fall2017/Lab3_template/DE0_NANO.v Line: 61
    Warning (13040): bidirectional pin "GPIO_1_D[19]" has no driver File: C:/Users/lab user/Desktop/ECE3400_Fall2017/Lab3_template/DE0_NANO.v Line: 61
    Warning (13040): bidirectional pin "GPIO_1_D[20]" has no driver File: C:/Users/lab user/Desktop/ECE3400_Fall2017/Lab3_template/DE0_NANO.v Line: 61
    Warning (13040): bidirectional pin "GPIO_1_D[21]" has no driver File: C:/Users/lab user/Desktop/ECE3400_Fall2017/Lab3_template/DE0_NANO.v Line: 61
    Warning (13040): bidirectional pin "GPIO_1_D[22]" has no driver File: C:/Users/lab user/Desktop/ECE3400_Fall2017/Lab3_template/DE0_NANO.v Line: 61
    Warning (13040): bidirectional pin "GPIO_1_D[23]" has no driver File: C:/Users/lab user/Desktop/ECE3400_Fall2017/Lab3_template/DE0_NANO.v Line: 61
    Warning (13040): bidirectional pin "GPIO_1_D[24]" has no driver File: C:/Users/lab user/Desktop/ECE3400_Fall2017/Lab3_template/DE0_NANO.v Line: 61
    Warning (13040): bidirectional pin "GPIO_1_D[25]" has no driver File: C:/Users/lab user/Desktop/ECE3400_Fall2017/Lab3_template/DE0_NANO.v Line: 61
    Warning (13040): bidirectional pin "GPIO_1_D[26]" has no driver File: C:/Users/lab user/Desktop/ECE3400_Fall2017/Lab3_template/DE0_NANO.v Line: 61
    Warning (13040): bidirectional pin "GPIO_1_D[27]" has no driver File: C:/Users/lab user/Desktop/ECE3400_Fall2017/Lab3_template/DE0_NANO.v Line: 61
    Warning (13040): bidirectional pin "GPIO_1_D[28]" has no driver File: C:/Users/lab user/Desktop/ECE3400_Fall2017/Lab3_template/DE0_NANO.v Line: 61
    Warning (13040): bidirectional pin "GPIO_1_D[29]" has no driver File: C:/Users/lab user/Desktop/ECE3400_Fall2017/Lab3_template/DE0_NANO.v Line: 61
    Warning (13040): bidirectional pin "GPIO_1_D[30]" has no driver File: C:/Users/lab user/Desktop/ECE3400_Fall2017/Lab3_template/DE0_NANO.v Line: 61
    Warning (13040): bidirectional pin "GPIO_1_D[31]" has no driver File: C:/Users/lab user/Desktop/ECE3400_Fall2017/Lab3_template/DE0_NANO.v Line: 61
    Warning (13040): bidirectional pin "GPIO_1_D[32]" has no driver File: C:/Users/lab user/Desktop/ECE3400_Fall2017/Lab3_template/DE0_NANO.v Line: 61
    Warning (13040): bidirectional pin "GPIO_1_D[33]" has no driver File: C:/Users/lab user/Desktop/ECE3400_Fall2017/Lab3_template/DE0_NANO.v Line: 61
Warning (13032): The following tri-state nodes are fed by constants
    Warning (13033): The pin "GPIO_0_D[9]" is fed by GND File: C:/Users/lab user/Desktop/ECE3400_Fall2017/Lab3_template/DE0_NANO.v Line: 57
    Warning (13033): The pin "GPIO_0_D[11]" is fed by GND File: C:/Users/lab user/Desktop/ECE3400_Fall2017/Lab3_template/DE0_NANO.v Line: 57
    Warning (13033): The pin "GPIO_0_D[13]" is fed by GND File: C:/Users/lab user/Desktop/ECE3400_Fall2017/Lab3_template/DE0_NANO.v Line: 57
    Warning (13033): The pin "GPIO_0_D[21]" is fed by GND File: C:/Users/lab user/Desktop/ECE3400_Fall2017/Lab3_template/DE0_NANO.v Line: 57
    Warning (13033): The pin "GPIO_0_D[23]" is fed by GND File: C:/Users/lab user/Desktop/ECE3400_Fall2017/Lab3_template/DE0_NANO.v Line: 57
Warning (13009): TRI or OPNDRN buffers permanently enabled
    Warning (13010): Node "GPIO_0_D[5]~synth" File: C:/Users/lab user/Desktop/ECE3400_Fall2017/Lab3_template/DE0_NANO.v Line: 57
    Warning (13010): Node "GPIO_0_D[7]~synth" File: C:/Users/lab user/Desktop/ECE3400_Fall2017/Lab3_template/DE0_NANO.v Line: 57
    Warning (13010): Node "GPIO_0_D[15]~synth" File: C:/Users/lab user/Desktop/ECE3400_Fall2017/Lab3_template/DE0_NANO.v Line: 57
    Warning (13010): Node "GPIO_0_D[17]~synth" File: C:/Users/lab user/Desktop/ECE3400_Fall2017/Lab3_template/DE0_NANO.v Line: 57
    Warning (13010): Node "GPIO_0_D[19]~synth" File: C:/Users/lab user/Desktop/ECE3400_Fall2017/Lab3_template/DE0_NANO.v Line: 57
Warning (13024): Output pins are stuck at VCC or GND
    Warning (13410): Pin "LED[1]" is stuck at GND File: C:/Users/lab user/Desktop/ECE3400_Fall2017/Lab3_template/DE0_NANO.v Line: 48
    Warning (13410): Pin "LED[2]" is stuck at GND File: C:/Users/lab user/Desktop/ECE3400_Fall2017/Lab3_template/DE0_NANO.v Line: 48
    Warning (13410): Pin "LED[3]" is stuck at GND File: C:/Users/lab user/Desktop/ECE3400_Fall2017/Lab3_template/DE0_NANO.v Line: 48
    Warning (13410): Pin "LED[4]" is stuck at GND File: C:/Users/lab user/Desktop/ECE3400_Fall2017/Lab3_template/DE0_NANO.v Line: 48
    Warning (13410): Pin "LED[5]" is stuck at GND File: C:/Users/lab user/Desktop/ECE3400_Fall2017/Lab3_template/DE0_NANO.v Line: 48
    Warning (13410): Pin "LED[6]" is stuck at GND File: C:/Users/lab user/Desktop/ECE3400_Fall2017/Lab3_template/DE0_NANO.v Line: 48
    Warning (13410): Pin "LED[7]" is stuck at GND File: C:/Users/lab user/Desktop/ECE3400_Fall2017/Lab3_template/DE0_NANO.v Line: 48
Info (286030): Timing-Driven Synthesis is running
Info (16010): Generating hard_block partition "hard_block:auto_generated_inst"
    Info (16011): Adding 0 node(s), including 0 DDIO, 0 PLL, 0 transceiver and 0 LCELL
Warning (21074): Design contains 9 input pin(s) that do not drive logic
    Warning (15610): No output dependent on input pin "KEY[1]" File: C:/Users/lab user/Desktop/ECE3400_Fall2017/Lab3_template/DE0_NANO.v Line: 51
    Warning (15610): No output dependent on input pin "SW[0]" File: C:/Users/lab user/Desktop/ECE3400_Fall2017/Lab3_template/DE0_NANO.v Line: 54
    Warning (15610): No output dependent on input pin "SW[1]" File: C:/Users/lab user/Desktop/ECE3400_Fall2017/Lab3_template/DE0_NANO.v Line: 54
    Warning (15610): No output dependent on input pin "SW[2]" File: C:/Users/lab user/Desktop/ECE3400_Fall2017/Lab3_template/DE0_NANO.v Line: 54
    Warning (15610): No output dependent on input pin "SW[3]" File: C:/Users/lab user/Desktop/ECE3400_Fall2017/Lab3_template/DE0_NANO.v Line: 54
    Warning (15610): No output dependent on input pin "GPIO_0_IN[0]" File: C:/Users/lab user/Desktop/ECE3400_Fall2017/Lab3_template/DE0_NANO.v Line: 58
    Warning (15610): No output dependent on input pin "GPIO_0_IN[1]" File: C:/Users/lab user/Desktop/ECE3400_Fall2017/Lab3_template/DE0_NANO.v Line: 58
    Warning (15610): No output dependent on input pin "GPIO_1_IN[0]" File: C:/Users/lab user/Desktop/ECE3400_Fall2017/Lab3_template/DE0_NANO.v Line: 62
    Warning (15610): No output dependent on input pin "GPIO_1_IN[1]" File: C:/Users/lab user/Desktop/ECE3400_Fall2017/Lab3_template/DE0_NANO.v Line: 62
Info (21057): Implemented 169 device resources after synthesis - the final resource count might be different
    Info (21058): Implemented 11 input pins
    Info (21059): Implemented 8 output pins
    Info (21060): Implemented 68 bidirectional pins
    Info (21061): Implemented 82 logic cells
Info: Quartus Prime Analysis & Synthesis was successful. 0 errors, 101 warnings
    Info: Peak virtual memory: 764 megabytes
    Info: Processing ended: Mon Jun 19 20:10:05 2017
    Info: Elapsed time: 00:00:09
    Info: Total CPU time (on all processors): 00:00:21


